Technical Field
The present invention relates generally to memories and, in particular, to queue control for shared memory access.
Description of the Related Art
The efficient control of multiple accesses for shared objects from processes and threads is one of the critical challenges in parallel computing systems. The use of cache on a processor side has been adopted in various systems and provides efficient controls within each cache coherent domain. However, remote memory accesses to the shared objects from outside of the cache coherent domain often become the critical paths in scaling out the system, in particular for sparse workloads. Thus, there is a need for an improved approach for shared memory access.